u01_avx2.hpp File Reference

#include <mckl/random/internal/common.hpp>
#include <mckl/random/internal/u01_generic.hpp>

Go to the source code of this file.

Classes
class	mckl::internal::U01AVX2Impl< UIntType, RealType, Lower, Upper, int >
class	mckl::internal::U01AVX2Impl< UIntType, double, Closed, Closed, 32 >
class	mckl::internal::U01AVX2Impl< UIntType, double, Closed, Closed, 64 >
class	mckl::internal::U01AVX2Impl< UIntType, double, Closed, Open, 32 >
class	mckl::internal::U01AVX2Impl< UIntType, double, Closed, Open, 64 >
class	mckl::internal::U01AVX2Impl< UIntType, double, Open, Closed, 32 >
class	mckl::internal::U01AVX2Impl< UIntType, double, Open, Closed, 64 >
class	mckl::internal::U01AVX2Impl< UIntType, double, Open, Open, 32 >
class	mckl::internal::U01AVX2Impl< UIntType, double, Open, Open, 64 >
class	mckl::internal::U01AVX2Impl< UIntType, float, Closed, Closed, 32 >
class	mckl::internal::U01AVX2Impl< UIntType, float, Closed, Open, 32 >
class	mckl::internal::U01AVX2Impl< UIntType, float, Open, Closed, 32 >
class	mckl::internal::U01AVX2Impl< UIntType, float, Open, Open, 32 >
class	mckl::internal::U01AVX2ImplBase< UIntType, RealType, Lower, Upper >
class	mckl::internal::U01CanonicalAVX2Impl< UIntType, RealType, Q, int >
class	mckl::internal::U01CanonicalAVX2Impl< UIntType, double, 1, 64 >
class	mckl::internal::U01CanonicalAVX2Impl< UIntType, double, 2, 32 >
class	mckl::internal::U01CanonicalAVX2Impl< UIntType, float, 1, 32 >
class	mckl::internal::U01CanonicalAVX2ImplBase< UIntType, RealType, Q >

Namespaces
	mckl
	mckl::internal

Macros
#define	MCKL_RANDOM_INTERNAL_U01_AVX2_ADD_PD(a)
#define	MCKL_RANDOM_INTERNAL_U01_AVX2_ADD_PS(a)
#define	MCKL_RANDOM_INTERNAL_U01_AVX2_AND1ADD_EPI32
#define	MCKL_RANDOM_INTERNAL_U01_AVX2_AND1ADD_EPI64
#define	MCKL_RANDOM_INTERNAL_U01_AVX2_CVTEPU32_PS
#define	MCKL_RANDOM_INTERNAL_U01_AVX2_CVTEPU32_PS_31
#define	MCKL_RANDOM_INTERNAL_U01_AVX2_CVTEPU64_PD
#define	MCKL_RANDOM_INTERNAL_U01_AVX2_CVTEPU64_PD_52
#define	MCKL_RANDOM_INTERNAL_U01_AVX2_FMADD_PD(a, b)
#define	MCKL_RANDOM_INTERNAL_U01_AVX2_FMADD_PS(a, b)
#define	MCKL_RANDOM_INTERNAL_U01_AVX2_LOADU_SI256(u)
#define	MCKL_RANDOM_INTERNAL_U01_AVX2_LOADU_SI256_CVTEPU32_EPI64(u)
#define	MCKL_RANDOM_INTERNAL_U01_AVX2_MUL_PD(a)
#define	MCKL_RANDOM_INTERNAL_U01_AVX2_MUL_PS(a)
#define	MCKL_RANDOM_INTERNAL_U01_AVX2_SLLI_EPI32(imm8)
#define	MCKL_RANDOM_INTERNAL_U01_AVX2_SLLI_EPI64(imm8)
#define	MCKL_RANDOM_INTERNAL_U01_AVX2_SRLI_EPI32(imm8)
#define	MCKL_RANDOM_INTERNAL_U01_AVX2_SRLI_EPI64(imm8)
#define	MCKL_RANDOM_INTERNAL_U01_AVX2_STOREU_PD(r)
#define	MCKL_RANDOM_INTERNAL_U01_AVX2_STOREU_PS(r)

Macro Definition Documentation

MCKL_RANDOM_INTERNAL_U01_AVX2_ADD_PD

#define MCKL_RANDOM_INTERNAL_U01_AVX2_ADD_PD

(

a

)

Value:

ymm0 = _mm256_castpd_si256(_mm256_add_pd(_mm256_castsi256_pd(ymm0), a));  \
    ymm1 = _mm256_castpd_si256(_mm256_add_pd(_mm256_castsi256_pd(ymm1), a));  \
    ymm2 = _mm256_castpd_si256(_mm256_add_pd(_mm256_castsi256_pd(ymm2), a));  \
    ymm3 = _mm256_castpd_si256(_mm256_add_pd(_mm256_castsi256_pd(ymm3), a));  \
    ymm4 = _mm256_castpd_si256(_mm256_add_pd(_mm256_castsi256_pd(ymm4), a));  \
    ymm5 = _mm256_castpd_si256(_mm256_add_pd(_mm256_castsi256_pd(ymm5), a));  \
    ymm6 = _mm256_castpd_si256(_mm256_add_pd(_mm256_castsi256_pd(ymm6), a));  \
    ymm7 = _mm256_castpd_si256(_mm256_add_pd(_mm256_castsi256_pd(ymm7), a));

Definition at line 461 of file u01_avx2.hpp.

MCKL_RANDOM_INTERNAL_U01_AVX2_ADD_PS

#define MCKL_RANDOM_INTERNAL_U01_AVX2_ADD_PS

(

a

)

Value:

ymm0 = _mm256_castps_si256(_mm256_add_ps(_mm256_castsi256_ps(ymm0), a));  \
    ymm1 = _mm256_castps_si256(_mm256_add_ps(_mm256_castsi256_ps(ymm1), a));  \
    ymm2 = _mm256_castps_si256(_mm256_add_ps(_mm256_castsi256_ps(ymm2), a));  \
    ymm3 = _mm256_castps_si256(_mm256_add_ps(_mm256_castsi256_ps(ymm3), a));  \
    ymm4 = _mm256_castps_si256(_mm256_add_ps(_mm256_castsi256_ps(ymm4), a));  \
    ymm5 = _mm256_castps_si256(_mm256_add_ps(_mm256_castsi256_ps(ymm5), a));  \
    ymm6 = _mm256_castps_si256(_mm256_add_ps(_mm256_castsi256_ps(ymm6), a));  \
    ymm7 = _mm256_castps_si256(_mm256_add_ps(_mm256_castsi256_ps(ymm7), a));

Definition at line 451 of file u01_avx2.hpp.

MCKL_RANDOM_INTERNAL_U01_AVX2_AND1ADD_EPI32

#define MCKL_RANDOM_INTERNAL_U01_AVX2_AND1ADD_EPI32

Value:

const __m256i mask = _mm256_set1_epi32(1);                                \
    ymm0 = _mm256_add_epi32(ymm0, _mm256_and_si256(ymm0, mask));              \
    ymm1 = _mm256_add_epi32(ymm1, _mm256_and_si256(ymm1, mask));              \
    ymm2 = _mm256_add_epi32(ymm2, _mm256_and_si256(ymm2, mask));              \
    ymm3 = _mm256_add_epi32(ymm3, _mm256_and_si256(ymm3, mask));              \
    ymm4 = _mm256_add_epi32(ymm4, _mm256_and_si256(ymm4, mask));              \
    ymm5 = _mm256_add_epi32(ymm5, _mm256_and_si256(ymm5, mask));              \
    ymm6 = _mm256_add_epi32(ymm6, _mm256_and_si256(ymm6, mask));              \
    ymm7 = _mm256_add_epi32(ymm7, _mm256_and_si256(ymm7, mask));

Definition at line 82 of file u01_avx2.hpp.

MCKL_RANDOM_INTERNAL_U01_AVX2_AND1ADD_EPI64

#define MCKL_RANDOM_INTERNAL_U01_AVX2_AND1ADD_EPI64

Value:

const __m256i mask = _mm256_set1_epi64x(1);                               \
    ymm0 = _mm256_add_epi64(ymm0, _mm256_and_si256(ymm0, mask));              \
    ymm1 = _mm256_add_epi64(ymm1, _mm256_and_si256(ymm1, mask));              \
    ymm2 = _mm256_add_epi64(ymm2, _mm256_and_si256(ymm2, mask));              \
    ymm3 = _mm256_add_epi64(ymm3, _mm256_and_si256(ymm3, mask));              \
    ymm4 = _mm256_add_epi64(ymm4, _mm256_and_si256(ymm4, mask));              \
    ymm5 = _mm256_add_epi64(ymm5, _mm256_and_si256(ymm5, mask));              \
    ymm6 = _mm256_add_epi64(ymm6, _mm256_and_si256(ymm6, mask));              \
    ymm7 = _mm256_add_epi64(ymm7, _mm256_and_si256(ymm7, mask));

Definition at line 93 of file u01_avx2.hpp.

MCKL_RANDOM_INTERNAL_U01_AVX2_CVTEPU32_PS

#define MCKL_RANDOM_INTERNAL_U01_AVX2_CVTEPU32_PS

Definition at line 156 of file u01_avx2.hpp.

MCKL_RANDOM_INTERNAL_U01_AVX2_CVTEPU32_PS_31

#define MCKL_RANDOM_INTERNAL_U01_AVX2_CVTEPU32_PS_31

Value:

ymm0 = _mm256_castps_si256(_mm256_cvtepi32_ps(ymm0));                     \
    ymm1 = _mm256_castps_si256(_mm256_cvtepi32_ps(ymm1));                     \
    ymm2 = _mm256_castps_si256(_mm256_cvtepi32_ps(ymm2));                     \
    ymm3 = _mm256_castps_si256(_mm256_cvtepi32_ps(ymm3));                     \
    ymm4 = _mm256_castps_si256(_mm256_cvtepi32_ps(ymm4));                     \
    ymm5 = _mm256_castps_si256(_mm256_cvtepi32_ps(ymm5));                     \
    ymm6 = _mm256_castps_si256(_mm256_cvtepi32_ps(ymm6));                     \
    ymm7 = _mm256_castps_si256(_mm256_cvtepi32_ps(ymm7));

Definition at line 144 of file u01_avx2.hpp.

MCKL_RANDOM_INTERNAL_U01_AVX2_CVTEPU64_PD

#define MCKL_RANDOM_INTERNAL_U01_AVX2_CVTEPU64_PD

Definition at line 313 of file u01_avx2.hpp.

MCKL_RANDOM_INTERNAL_U01_AVX2_CVTEPU64_PD_52

#define MCKL_RANDOM_INTERNAL_U01_AVX2_CVTEPU64_PD_52

Value:

const __m256d c = _mm256_set1_pd(Pow2<double, 52>::value);                \
    ymm0 = _mm256_add_epi64(ymm0, _mm256_castpd_si256(c));                    \
    ymm1 = _mm256_add_epi64(ymm1, _mm256_castpd_si256(c));                    \
    ymm2 = _mm256_add_epi64(ymm2, _mm256_castpd_si256(c));                    \
    ymm3 = _mm256_add_epi64(ymm3, _mm256_castpd_si256(c));                    \
    ymm4 = _mm256_add_epi64(ymm4, _mm256_castpd_si256(c));                    \
    ymm5 = _mm256_add_epi64(ymm5, _mm256_castpd_si256(c));                    \
    ymm6 = _mm256_add_epi64(ymm6, _mm256_castpd_si256(c));                    \
    ymm7 = _mm256_add_epi64(ymm7, _mm256_castpd_si256(c));                    \
    ymm0 = _mm256_castpd_si256(_mm256_sub_pd(_mm256_castsi256_pd(ymm0), c));  \
    ymm1 = _mm256_castpd_si256(_mm256_sub_pd(_mm256_castsi256_pd(ymm1), c));  \
    ymm2 = _mm256_castpd_si256(_mm256_sub_pd(_mm256_castsi256_pd(ymm2), c));  \
    ymm3 = _mm256_castpd_si256(_mm256_sub_pd(_mm256_castsi256_pd(ymm3), c));  \
    ymm4 = _mm256_castpd_si256(_mm256_sub_pd(_mm256_castsi256_pd(ymm4), c));  \
    ymm5 = _mm256_castpd_si256(_mm256_sub_pd(_mm256_castsi256_pd(ymm5), c));  \
    ymm6 = _mm256_castpd_si256(_mm256_sub_pd(_mm256_castsi256_pd(ymm6), c));  \
    ymm7 = _mm256_castpd_si256(_mm256_sub_pd(_mm256_castsi256_pd(ymm7), c));

Definition at line 292 of file u01_avx2.hpp.

MCKL_RANDOM_INTERNAL_U01_AVX2_FMADD_PD

#define MCKL_RANDOM_INTERNAL_U01_AVX2_FMADD_PD	(		a,
			b
	)

Value:

ymm0 = _mm256_castpd_si256(                                               \
        _mm256_fmadd_pd(_mm256_castsi256_pd(ymm0), a, b));                    \
    ymm1 = _mm256_castpd_si256(                                               \
        _mm256_fmadd_pd(_mm256_castsi256_pd(ymm1), a, b));                    \
    ymm2 = _mm256_castpd_si256(                                               \
        _mm256_fmadd_pd(_mm256_castsi256_pd(ymm2), a, b));                    \
    ymm3 = _mm256_castpd_si256(                                               \
        _mm256_fmadd_pd(_mm256_castsi256_pd(ymm3), a, b));                    \
    ymm4 = _mm256_castpd_si256(                                               \
        _mm256_fmadd_pd(_mm256_castsi256_pd(ymm4), a, b));                    \
    ymm5 = _mm256_castpd_si256(                                               \
        _mm256_fmadd_pd(_mm256_castsi256_pd(ymm5), a, b));                    \
    ymm6 = _mm256_castpd_si256(                                               \
        _mm256_fmadd_pd(_mm256_castsi256_pd(ymm6), a, b));                    \
    ymm7 = _mm256_castpd_si256(                                               \
        _mm256_fmadd_pd(_mm256_castsi256_pd(ymm7), a, b));

Definition at line 511 of file u01_avx2.hpp.

MCKL_RANDOM_INTERNAL_U01_AVX2_FMADD_PS

#define MCKL_RANDOM_INTERNAL_U01_AVX2_FMADD_PS	(		a,
			b
	)

Value:

ymm0 = _mm256_castps_si256(                                               \
        _mm256_fmadd_ps(_mm256_castsi256_ps(ymm0), a, b));                    \
    ymm1 = _mm256_castps_si256(                                               \
        _mm256_fmadd_ps(_mm256_castsi256_ps(ymm1), a, b));                    \
    ymm2 = _mm256_castps_si256(                                               \
        _mm256_fmadd_ps(_mm256_castsi256_ps(ymm2), a, b));                    \
    ymm3 = _mm256_castps_si256(                                               \
        _mm256_fmadd_ps(_mm256_castsi256_ps(ymm3), a, b));                    \
    ymm4 = _mm256_castps_si256(                                               \
        _mm256_fmadd_ps(_mm256_castsi256_ps(ymm4), a, b));                    \
    ymm5 = _mm256_castps_si256(                                               \
        _mm256_fmadd_ps(_mm256_castsi256_ps(ymm5), a, b));                    \
    ymm6 = _mm256_castps_si256(                                               \
        _mm256_fmadd_ps(_mm256_castsi256_ps(ymm6), a, b));                    \
    ymm7 = _mm256_castps_si256(                                               \
        _mm256_fmadd_ps(_mm256_castsi256_ps(ymm7), a, b));

Definition at line 493 of file u01_avx2.hpp.

MCKL_RANDOM_INTERNAL_U01_AVX2_LOADU_SI256

#define MCKL_RANDOM_INTERNAL_U01_AVX2_LOADU_SI256

(

u

)

Value:

const __m256i *uptr = reinterpret_cast<const __m256i *>(u);               \
    __m256i ymm0 = _mm256_loadu_si256(uptr++);                                \
    __m256i ymm1 = _mm256_loadu_si256(uptr++);                                \
    __m256i ymm2 = _mm256_loadu_si256(uptr++);                                \
    __m256i ymm3 = _mm256_loadu_si256(uptr++);                                \
    __m256i ymm4 = _mm256_loadu_si256(uptr++);                                \
    __m256i ymm5 = _mm256_loadu_si256(uptr++);                                \
    __m256i ymm6 = _mm256_loadu_si256(uptr++);                                \
    __m256i ymm7 = _mm256_loadu_si256(uptr++);

Definition at line 40 of file u01_avx2.hpp.

MCKL_RANDOM_INTERNAL_U01_AVX2_LOADU_SI256_CVTEPU32_EPI64

#define MCKL_RANDOM_INTERNAL_U01_AVX2_LOADU_SI256_CVTEPU32_EPI64

(

u

)

Value:

const __m128i *uptr = reinterpret_cast<const __m128i *>(u);               \
    __m256i ymm0 = _mm256_cvtepu32_epi64(_mm_loadu_si128(uptr++));            \
    __m256i ymm1 = _mm256_cvtepu32_epi64(_mm_loadu_si128(uptr++));            \
    __m256i ymm2 = _mm256_cvtepu32_epi64(_mm_loadu_si128(uptr++));            \
    __m256i ymm3 = _mm256_cvtepu32_epi64(_mm_loadu_si128(uptr++));            \
    __m256i ymm4 = _mm256_cvtepu32_epi64(_mm_loadu_si128(uptr++));            \
    __m256i ymm5 = _mm256_cvtepu32_epi64(_mm_loadu_si128(uptr++));            \
    __m256i ymm6 = _mm256_cvtepu32_epi64(_mm_loadu_si128(uptr++));            \
    __m256i ymm7 = _mm256_cvtepu32_epi64(_mm_loadu_si128(uptr++));

Definition at line 51 of file u01_avx2.hpp.

MCKL_RANDOM_INTERNAL_U01_AVX2_MUL_PD

#define MCKL_RANDOM_INTERNAL_U01_AVX2_MUL_PD

(

a

)

Value:

ymm0 = _mm256_castpd_si256(_mm256_mul_pd(_mm256_castsi256_pd(ymm0), a));  \
    ymm1 = _mm256_castpd_si256(_mm256_mul_pd(_mm256_castsi256_pd(ymm1), a));  \
    ymm2 = _mm256_castpd_si256(_mm256_mul_pd(_mm256_castsi256_pd(ymm2), a));  \
    ymm3 = _mm256_castpd_si256(_mm256_mul_pd(_mm256_castsi256_pd(ymm3), a));  \
    ymm4 = _mm256_castpd_si256(_mm256_mul_pd(_mm256_castsi256_pd(ymm4), a));  \
    ymm5 = _mm256_castpd_si256(_mm256_mul_pd(_mm256_castsi256_pd(ymm5), a));  \
    ymm6 = _mm256_castpd_si256(_mm256_mul_pd(_mm256_castsi256_pd(ymm6), a));  \
    ymm7 = _mm256_castpd_si256(_mm256_mul_pd(_mm256_castsi256_pd(ymm7), a));

Definition at line 481 of file u01_avx2.hpp.

MCKL_RANDOM_INTERNAL_U01_AVX2_MUL_PS

#define MCKL_RANDOM_INTERNAL_U01_AVX2_MUL_PS

(

a

)

Value:

ymm0 = _mm256_castps_si256(_mm256_mul_ps(_mm256_castsi256_ps(ymm0), a));  \
    ymm1 = _mm256_castps_si256(_mm256_mul_ps(_mm256_castsi256_ps(ymm1), a));  \
    ymm2 = _mm256_castps_si256(_mm256_mul_ps(_mm256_castsi256_ps(ymm2), a));  \
    ymm3 = _mm256_castps_si256(_mm256_mul_ps(_mm256_castsi256_ps(ymm3), a));  \
    ymm4 = _mm256_castps_si256(_mm256_mul_ps(_mm256_castsi256_ps(ymm4), a));  \
    ymm5 = _mm256_castps_si256(_mm256_mul_ps(_mm256_castsi256_ps(ymm5), a));  \
    ymm6 = _mm256_castps_si256(_mm256_mul_ps(_mm256_castsi256_ps(ymm6), a));  \
    ymm7 = _mm256_castps_si256(_mm256_mul_ps(_mm256_castsi256_ps(ymm7), a));

Definition at line 471 of file u01_avx2.hpp.

MCKL_RANDOM_INTERNAL_U01_AVX2_SLLI_EPI32

#define MCKL_RANDOM_INTERNAL_U01_AVX2_SLLI_EPI32

(

imm8

)

Value:

ymm0 = _mm256_slli_epi32(ymm0, imm8);                                     \
    ymm1 = _mm256_slli_epi32(ymm1, imm8);                                     \
    ymm2 = _mm256_slli_epi32(ymm2, imm8);                                     \
    ymm3 = _mm256_slli_epi32(ymm3, imm8);                                     \
    ymm4 = _mm256_slli_epi32(ymm4, imm8);                                     \
    ymm5 = _mm256_slli_epi32(ymm5, imm8);                                     \
    ymm6 = _mm256_slli_epi32(ymm6, imm8);                                     \
    ymm7 = _mm256_slli_epi32(ymm7, imm8);

Definition at line 104 of file u01_avx2.hpp.

MCKL_RANDOM_INTERNAL_U01_AVX2_SLLI_EPI64

#define MCKL_RANDOM_INTERNAL_U01_AVX2_SLLI_EPI64

(

imm8

)

Value:

ymm0 = _mm256_slli_epi64(ymm0, imm8);                                     \
    ymm1 = _mm256_slli_epi64(ymm1, imm8);                                     \
    ymm2 = _mm256_slli_epi64(ymm2, imm8);                                     \
    ymm3 = _mm256_slli_epi64(ymm3, imm8);                                     \
    ymm4 = _mm256_slli_epi64(ymm4, imm8);                                     \
    ymm5 = _mm256_slli_epi64(ymm5, imm8);                                     \
    ymm6 = _mm256_slli_epi64(ymm6, imm8);                                     \
    ymm7 = _mm256_slli_epi64(ymm7, imm8);

Definition at line 124 of file u01_avx2.hpp.

MCKL_RANDOM_INTERNAL_U01_AVX2_SRLI_EPI32

#define MCKL_RANDOM_INTERNAL_U01_AVX2_SRLI_EPI32

(

imm8

)

Value:

ymm0 = _mm256_srli_epi32(ymm0, imm8);                                     \
    ymm1 = _mm256_srli_epi32(ymm1, imm8);                                     \
    ymm2 = _mm256_srli_epi32(ymm2, imm8);                                     \
    ymm3 = _mm256_srli_epi32(ymm3, imm8);                                     \
    ymm4 = _mm256_srli_epi32(ymm4, imm8);                                     \
    ymm5 = _mm256_srli_epi32(ymm5, imm8);                                     \
    ymm6 = _mm256_srli_epi32(ymm6, imm8);                                     \
    ymm7 = _mm256_srli_epi32(ymm7, imm8);

Definition at line 114 of file u01_avx2.hpp.

MCKL_RANDOM_INTERNAL_U01_AVX2_SRLI_EPI64

#define MCKL_RANDOM_INTERNAL_U01_AVX2_SRLI_EPI64

(

imm8

)

Value:

ymm0 = _mm256_srli_epi64(ymm0, imm8);                                     \
    ymm1 = _mm256_srli_epi64(ymm1, imm8);                                     \
    ymm2 = _mm256_srli_epi64(ymm2, imm8);                                     \
    ymm3 = _mm256_srli_epi64(ymm3, imm8);                                     \
    ymm4 = _mm256_srli_epi64(ymm4, imm8);                                     \
    ymm5 = _mm256_srli_epi64(ymm5, imm8);                                     \
    ymm6 = _mm256_srli_epi64(ymm6, imm8);                                     \
    ymm7 = _mm256_srli_epi64(ymm7, imm8);

Definition at line 134 of file u01_avx2.hpp.

MCKL_RANDOM_INTERNAL_U01_AVX2_STOREU_PD

#define MCKL_RANDOM_INTERNAL_U01_AVX2_STOREU_PD

(

r

)

Value:

_mm256_storeu_pd(r + 0x00, _mm256_castsi256_pd(ymm0));                    \
    _mm256_storeu_pd(r + 0x04, _mm256_castsi256_pd(ymm1));                    \
    _mm256_storeu_pd(r + 0x08, _mm256_castsi256_pd(ymm2));                    \
    _mm256_storeu_pd(r + 0x0C, _mm256_castsi256_pd(ymm3));                    \
    _mm256_storeu_pd(r + 0x10, _mm256_castsi256_pd(ymm4));                    \
    _mm256_storeu_pd(r + 0x14, _mm256_castsi256_pd(ymm5));                    \
    _mm256_storeu_pd(r + 0x18, _mm256_castsi256_pd(ymm6));                    \
    _mm256_storeu_pd(r + 0x1C, _mm256_castsi256_pd(ymm7));

Definition at line 72 of file u01_avx2.hpp.

MCKL_RANDOM_INTERNAL_U01_AVX2_STOREU_PS

#define MCKL_RANDOM_INTERNAL_U01_AVX2_STOREU_PS

(

r

)

Value:

_mm256_storeu_ps(r + 0x00, _mm256_castsi256_ps(ymm0));                    \
    _mm256_storeu_ps(r + 0x08, _mm256_castsi256_ps(ymm1));                    \
    _mm256_storeu_ps(r + 0x10, _mm256_castsi256_ps(ymm2));                    \
    _mm256_storeu_ps(r + 0x18, _mm256_castsi256_ps(ymm3));                    \
    _mm256_storeu_ps(r + 0x20, _mm256_castsi256_ps(ymm4));                    \
    _mm256_storeu_ps(r + 0x28, _mm256_castsi256_ps(ymm5));                    \
    _mm256_storeu_ps(r + 0x30, _mm256_castsi256_ps(ymm6));                    \
    _mm256_storeu_ps(r + 0x38, _mm256_castsi256_ps(ymm7));

Definition at line 62 of file u01_avx2.hpp.